| ??? 06/19/08 00:02 Read: times |
#156024 - Oy Responding to: ???'s previous message |
Richard Erlacher said:
I have problems with VHDL because you can't specify some things with the most widely used data type. This means you have to add type conversion calls to the code where you want to specify things in decimal. That often makes the listings quite murky. I'd prefer to keep it simple. Two comments: a) you can specify pretty much everything in the "most widely used data type" (which I assume that you mean std_logic and std_logic_vector). b) Type conversions are necessary because it is a strongly-typed language. But I think that you're not fluent enough in VHDL to know when you can just use integer types and when you have to use std_logic_vector. Hint: FPGA tools like std_logic and std_logic_vector at the chip's I/O ports, but there is no reason why internal stuff has to be SLV. I have a bunch of modules where the inputs and outputs are unsigned() and I do the math on those signals without type conversions. Answer the question I posed in another post in this thread, and perhaps it'll be clear why there are different types and type-conversion functions. Also NB: NEVER use the std_logic_arith/std_logic_(un)signed libraries. Instead, use numeric_std. The latter's type-conversion functions make a lot more sense, and you can actually mix signed and unsigned representations in the same module. -a |
