Perhaps it's just a problem in the schematic editor, which I use for reasons I've already stated a few times.

What I frequently do is to generate a block symbol for a VHDL module, which I can document so it's palatable to my clients, and then use it in a block diagram. That way the reviewers can see what the general layout of the circuit is, and can also examine the details and timing of the content of those task-specific blocks.

Unfortunately, starting with release 7, their schematic editor was pretty much useless.

In v9.x, it's still very cumbersome because in the switch between operating modes (I hate mode editors!) it doesn't bring the context with it, as it did in pre-v7 releases, so you have to reconfigure the display each time you move from, say, draw a line, to insert a symbol. This makes a simple block diagram that would ordinarily take less than half-an-hour to create take a day or more. The result is that I use either the old stuff or ALTERA.

I've never been able to get ModelSim to work in release 9.

Fortunately, I use mainly the 5-volt compatible 9500 and Spartan-2 series and the 5-volt tolerant SP-II and XPLA3's.

RE