| ??? 06/01/08 12:50 Read: times |
#155344 - Is the synthesis really wrong, or just the RTL? Responding to: ???'s previous message |
Jez said:
The reason I know that the synthesis is wrong is by following the logic thought the rtl viewer built into ISE and it was possible to see that a state where a register should have been latched had simply not been synthesised. I think I've already established myself on this forum as not an expert on this subject. If not, I'll state it clearly for the record: I am not an expert on this subject! However, when I was messing around with verion ISE 9.2.03i a few months ago, I'm sure I saw tiny, trivial cases where the RTL schematic was obviously wrong, yet the so-called "technology schematic" appeared to be correct and the design worked, both in the simulator and on the actual hardware. I remember concluding that the RTL schematic couldn't be trusted, and basically ignored it after that. I even mentioned this at the time, here. So I'm wondering -- are you saying you think that the synthesis is wrong because the RTL schematic looks wrong? If so, do you have any evidence that the RTL view actually matches what got synthsized? My experience was that it doesn't always. -- Russ |
