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???
06/18/08 17:32
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#156009 - Thanks for the "spiritual guidance" ...
Responding to: ???'s previous message
This was exactly what I was looking for, namely, a simple answer to the question of how to specify a value in decimal form so people could understand it easily.

Actually, I've had to rely on a number of texts on the subject and, though they have specified a pretty ugly sort of type-conversion that they have in common, their syntax is apparently unpalatable to ModelSim.

I've snagged a few items from the www, and they all point to the same method, which the ISE doesn't seem to like.

My conceptions of what the language will/won't do are not totally preconceived, but, rather, are the product of searching through a significant number of texts, including all the ones available at the university library (and those available through interlibrary loan) and a few that I've actually bought (Ashenden's VHDL guide for Designers, for example, and that initial book I got over a decade ago when I took the course that Cypress offered.

I'm quite sure that none of them discuss the use of decimal numbers. Perhaps that's because it's "obvious" but it's not ... at least not to me.

Since it's always served, so long as I stick to HEX or binary specification of, say, boundary values, etc. It hasn't been much of a problem for me, but I have lamented that each time I did that, I had to comment the code to indicate what the decimal value was.

If you say that ModelSim will understand what I mean (and I will verify that I understand you via simulation) I should just be able to specify a terminal count in an otherwise binary counter as "999999" and have it transition to zero at that point.

I had always considered that it might be one of those "assume the obvious" cases, but, since I didn't find anything expressly stating how to specify decimal values, I didn't do it. I simply don't believe in doing what the doc's don't say, explicitly, is valid. Perhaps I've simply used the wrong references.

RE



List of 51 messages in thread
TopicAuthorDate
xilinx ISE 10.1 is broken            01/01/70 00:00      
   a lot of their stuff has been broken lately ...            01/01/70 00:00      
   broken!            01/01/70 00:00      
      JSM            01/01/70 00:00      
   ah ha well.....            01/01/70 00:00      
      v7 was a stab at a rewrite, as was v8            01/01/70 00:00      
         Schematic?            01/01/70 00:00      
            Once upon a time ...            01/01/70 00:00      
               jesus            01/01/70 00:00      
                  it's not the technology ...            01/01/70 00:00      
                     kind of            01/01/70 00:00      
                        Is the synthesis really wrong, or just the RTL?            01/01/70 00:00      
                           nope            01/01/70 00:00      
                              Thanks            01/01/70 00:00      
                                 Anyway            01/01/70 00:00      
                        schematic versus block diagram            01/01/70 00:00      
                        I have to take exception            01/01/70 00:00      
                           gates            01/01/70 00:00      
                  Not quite            01/01/70 00:00      
               wow talk about out of date....            01/01/70 00:00      
                  Not so fast, there, Pilgrim ...            01/01/70 00:00      
                     various ways to do that            01/01/70 00:00      
                        I'm not sure that applies ... Jez            01/01/70 00:00      
                           Can I suggest            01/01/70 00:00      
                              Thanks for the "spiritual guidance" ...            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                    It's about readability            01/01/70 00:00      
                                       readability            01/01/70 00:00      
                                          also re: readability            01/01/70 00:00      
                                       re: readability            01/01/70 00:00      
                                       type conversion is a pain            01/01/70 00:00      
                                          Yes it's a pain, and it's not well explained.            01/01/70 00:00      
                                             bzzzzzzzzzzzt!            01/01/70 00:00      
                                                Its all about the doc            01/01/70 00:00      
                                                   why the different types?            01/01/70 00:00      
                                                      This is good stuff!            01/01/70 00:00      
                                                         obscurity            01/01/70 00:00      
                                                            Nearly every package has a manual            01/01/70 00:00      
                                                               buffer mode ports            01/01/70 00:00      
                                                                  buried macrocells too            01/01/70 00:00      
                                                                     experts            01/01/70 00:00      
                                                                        Yes, it's about the "experts."            01/01/70 00:00      
                                                   endianity            01/01/70 00:00      
                                                      endianity drives me to insanity ...            01/01/70 00:00      
                                                         HDL wins            01/01/70 00:00      
                     no....            01/01/70 00:00      
                  An interesting dichotomy...            01/01/70 00:00      
                     I don\'t follow ...            01/01/70 00:00      
                        Oy            01/01/70 00:00      
      not synthesizing correctly            01/01/70 00:00      

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