| ??? 06/18/08 02:26 Read: times |
#155984 - I have to take exception Responding to: ???'s previous message |
Jez Smith said:
To some extent Richard is right when he says that schematics are useful when you want to show how a system works, the real problem comes when you get designs which are partly schematics and partly VHDL or verilog, then they get really hard to maintain.
Currently the largest design we use has the equivalent of 1.7 million gates of logic all coded as vhdl but I can still draw a top level schematic of the design when I want to talk to someone about how it all works or proposed changes. When you talk about those 1.7 million gates, keep in mind that the XILINX marketeers talk about a 3-input AND as being three gates, and a 'D' flipflop, which I learned in school was about 6 gates, as 14. The path I've chosen for myself involves composing blocks containing either VHDL, which can be quite concise, or, can be quite verbose in some cases, or a schematic. Those blocks, sometimes containing quite a bit of hierarchy, are then placed in a top-level drawing, which is presented for review, and the internals of those blocks are presented in schematic form, if there's a hierarchy or in simulated VHDL descriptions, for the benefit of those who don't speak VHDL, which happens to include the majority of my clients. I find this supremely maintainable, as the symbols, whether created by me or extracted from the XILINX libraries, are well documented. This allows me to have my designs reviewed by the folks who want to do it and not a bunch of purportedly VHDL-literate consultants they've hired, who seldom understand, and even less often agree on, what it all does. Normally, since the guys I most often work for are of approximately the same vintage as my own, they can all read and understand a pretty large schematic in very little time. They all understand the notion of a "counter" or a "decoder" or a gate. It's not difficult to get through a 50000 gate review in less than half a day. With VHDL, it takes that long just to read it, let alone understand it, so the block diagram is absolutely necessary. Moore and Mealy state machines do have practical differences which make them useful in different applications, rather than being simply academic.
The reason I know that the synthesis is wrong is by following the logic thought the rtl viewer built into ISE and it was possible to see that a state where a register should have been latched had simply not been synthesised. I've not had that experience, Jez, and I've not yet tried out v10.whatever. I'm using the relatively bug-free v6.3.03 for the 5-volt tolerant Spartan-II's, XPLA3's, 9500's, etc and v9.2.04 for the current-generation FPGA's. They've gotten most of the real crap out of the schematic editor, though it still rearranges the screen for you when you aren't expecting it. That wastes lots of time looking for this tool or that. RE |
