the design didn't work when compiler under 10.1 when it compiled quite happily under earlier versions, and looking at the RTL viewer it was clear exactly why it didn't work, it had simply ignored a state machine transition.
basically with each new release they do try to bring the compiler/synthesis closer to the vhdl standard it is however impossible to test each and every possible situation.It is a highly complex piece of software and its quite amazing that it works at all.
Xilinx have passed my particular piece of code to the development team so they can try to see why its not synthesising properly.