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???
06/20/08 02:46
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#156057 - Yes it's a pain, and it's not well explained.
Responding to: ???'s previous message
Andy Peters said:
Richard said:
Actually, I've spent quite a lot of time doing what I needed to do with VHDL, and this business with type conversion has often been a pain.


As I've said, VHDL is a strongly-typed language, unlike Verilog, which is an unmitigated disaster when it comes to dealing with numbers.

But you still haven't answered my question. What is the decimal equivalent to the binary vector "10010110"? The answer makes it obvious why VHDL handles numbers as it does.

I don't know why that's an issue but if it's what it appears to be, namely a bit vector, then the first element is 1 which makes it a HEX 69, which is decimal 96+9 or 105.

I should further note that you can code your numbers however you want, and your simulator (I use ModelSim) can display a vector in any numeric base you wish. (It can even do a simple D-to-A conversion and show it as a waveform!)

-a


I agree about the simulator, and, in fact, that's made some things pass that might otherwise have failed.

What puzzles me is why so many textbooks on VHDL simply fail to discuss the business of the various data types and their purpose, and when they're of benefit, not to mention the business of translating from one to the other.

Running the counter in type natural is fine until you have to generate STD_LOGIC_VECTOR output from it because it's an address counter in a DMA Channel. Then, too, you'd want to decode various strobes from the low-order bits ... How would that work without type conversion?

Can you recommend of a text that actually goes into meaningful and exhaustive detail about when you'd want to use one type over another?

RE


List of 51 messages in thread
TopicAuthorDate
xilinx ISE 10.1 is broken            01/01/70 00:00      
   a lot of their stuff has been broken lately ...            01/01/70 00:00      
   broken!            01/01/70 00:00      
      JSM            01/01/70 00:00      
   ah ha well.....            01/01/70 00:00      
      v7 was a stab at a rewrite, as was v8            01/01/70 00:00      
         Schematic?            01/01/70 00:00      
            Once upon a time ...            01/01/70 00:00      
               jesus            01/01/70 00:00      
                  it's not the technology ...            01/01/70 00:00      
                     kind of            01/01/70 00:00      
                        Is the synthesis really wrong, or just the RTL?            01/01/70 00:00      
                           nope            01/01/70 00:00      
                              Thanks            01/01/70 00:00      
                                 Anyway            01/01/70 00:00      
                        schematic versus block diagram            01/01/70 00:00      
                        I have to take exception            01/01/70 00:00      
                           gates            01/01/70 00:00      
                  Not quite            01/01/70 00:00      
               wow talk about out of date....            01/01/70 00:00      
                  Not so fast, there, Pilgrim ...            01/01/70 00:00      
                     various ways to do that            01/01/70 00:00      
                        I'm not sure that applies ... Jez            01/01/70 00:00      
                           Can I suggest            01/01/70 00:00      
                              Thanks for the "spiritual guidance" ...            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                    It's about readability            01/01/70 00:00      
                                       readability            01/01/70 00:00      
                                          also re: readability            01/01/70 00:00      
                                       re: readability            01/01/70 00:00      
                                       type conversion is a pain            01/01/70 00:00      
                                          Yes it's a pain, and it's not well explained.            01/01/70 00:00      
                                             bzzzzzzzzzzzt!            01/01/70 00:00      
                                                Its all about the doc            01/01/70 00:00      
                                                   why the different types?            01/01/70 00:00      
                                                      This is good stuff!            01/01/70 00:00      
                                                         obscurity            01/01/70 00:00      
                                                            Nearly every package has a manual            01/01/70 00:00      
                                                               buffer mode ports            01/01/70 00:00      
                                                                  buried macrocells too            01/01/70 00:00      
                                                                     experts            01/01/70 00:00      
                                                                        Yes, it's about the "experts."            01/01/70 00:00      
                                                   endianity            01/01/70 00:00      
                                                      endianity drives me to insanity ...            01/01/70 00:00      
                                                         HDL wins            01/01/70 00:00      
                     no....            01/01/70 00:00      
                  An interesting dichotomy...            01/01/70 00:00      
                     I don\'t follow ...            01/01/70 00:00      
                        Oy            01/01/70 00:00      
      not synthesizing correctly            01/01/70 00:00      

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