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???
05/31/08 20:15
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#155334 - jesus
Responding to: ???'s previous message
Richard Erlacher said:
When people were smart enough to use a 22-cent CD4017 instead of a 50-dollar FPGA to implement a 10-stage one-hot, people did that with schematics.


Yeah, but you keep forgetting that my FPGA is doing more than just a counter. And what I do in my FPGA would take a whole rack full of SSI parts.

Nowadays, folks aren't that smart. They buy and sell things that only barely work, like cellphones, for example.


That's right, blame the technology and not the people doing the work.

Put a few old timers who learned how to read schematics in a room, and, within minutes they all agree on what the schematic means. Put a dozen HDL experts in a room with the 1000-page listing that an 'E' sheet of schematics represents, in a room, and after two months, you'll have at least 13 opinions. How can you work with that?


... and the amount of schematic pages that are equivalent to a 1000-page HDL listing is, what, 1000? 5000? 10000? Who the hell can keep track of that, much less verify it?

Give me a break. Really. It seems like the "experts" you've come across are not at advertised. There are tons of "experts" who do schematics which are completely inscrutable, and those "experts" probably don't even know how their own work functions after being away from it for a year.

For trivial designs, a schematic may be easier. For larger stuff, give me an HDL any time.

You DO realize that I was yanking your chain, and of course I got the expected response.

-a

List of 51 messages in thread
TopicAuthorDate
xilinx ISE 10.1 is broken            01/01/70 00:00      
   a lot of their stuff has been broken lately ...            01/01/70 00:00      
   broken!            01/01/70 00:00      
      JSM            01/01/70 00:00      
   ah ha well.....            01/01/70 00:00      
      v7 was a stab at a rewrite, as was v8            01/01/70 00:00      
         Schematic?            01/01/70 00:00      
            Once upon a time ...            01/01/70 00:00      
               jesus            01/01/70 00:00      
                  it's not the technology ...            01/01/70 00:00      
                     kind of            01/01/70 00:00      
                        Is the synthesis really wrong, or just the RTL?            01/01/70 00:00      
                           nope            01/01/70 00:00      
                              Thanks            01/01/70 00:00      
                                 Anyway            01/01/70 00:00      
                        schematic versus block diagram            01/01/70 00:00      
                        I have to take exception            01/01/70 00:00      
                           gates            01/01/70 00:00      
                  Not quite            01/01/70 00:00      
               wow talk about out of date....            01/01/70 00:00      
                  Not so fast, there, Pilgrim ...            01/01/70 00:00      
                     various ways to do that            01/01/70 00:00      
                        I'm not sure that applies ... Jez            01/01/70 00:00      
                           Can I suggest            01/01/70 00:00      
                              Thanks for the "spiritual guidance" ...            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                    It's about readability            01/01/70 00:00      
                                       readability            01/01/70 00:00      
                                          also re: readability            01/01/70 00:00      
                                       re: readability            01/01/70 00:00      
                                       type conversion is a pain            01/01/70 00:00      
                                          Yes it's a pain, and it's not well explained.            01/01/70 00:00      
                                             bzzzzzzzzzzzt!            01/01/70 00:00      
                                                Its all about the doc            01/01/70 00:00      
                                                   why the different types?            01/01/70 00:00      
                                                      This is good stuff!            01/01/70 00:00      
                                                         obscurity            01/01/70 00:00      
                                                            Nearly every package has a manual            01/01/70 00:00      
                                                               buffer mode ports            01/01/70 00:00      
                                                                  buried macrocells too            01/01/70 00:00      
                                                                     experts            01/01/70 00:00      
                                                                        Yes, it's about the "experts."            01/01/70 00:00      
                                                   endianity            01/01/70 00:00      
                                                      endianity drives me to insanity ...            01/01/70 00:00      
                                                         HDL wins            01/01/70 00:00      
                     no....            01/01/70 00:00      
                  An interesting dichotomy...            01/01/70 00:00      
                     I don\'t follow ...            01/01/70 00:00      
                        Oy            01/01/70 00:00      
      not synthesizing correctly            01/01/70 00:00      

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