Email: Password: Remember Me | Create Account (Free)

Back to Subject List

Old thread has been locked -- no new posts accepted in this thread
???
06/18/08 23:42
Read: times


 		 #156021 - gates
Responding to: ???'s previous message
Richard,

Yeah, we know that all of the FPGA companies have "marketing gates."

When talking about design size, we should ignore "gates" and instead use LUTs and SLICEs, which are exact numbers spit out by the tools after place and route completes.

-a

List of 51 messages in thread
TopicAuthorDate
xilinx ISE 10.1 is broken            01/01/70 00:00      
   a lot of their stuff has been broken lately ...            01/01/70 00:00      
   broken!            01/01/70 00:00      
      JSM            01/01/70 00:00      
   ah ha well.....            01/01/70 00:00      
      v7 was a stab at a rewrite, as was v8            01/01/70 00:00      
         Schematic?            01/01/70 00:00      
            Once upon a time ...            01/01/70 00:00      
               jesus            01/01/70 00:00      
                  it's not the technology ...            01/01/70 00:00      
                     kind of            01/01/70 00:00      
                        Is the synthesis really wrong, or just the RTL?            01/01/70 00:00      
                           nope            01/01/70 00:00      
                              Thanks            01/01/70 00:00      
                                 Anyway            01/01/70 00:00      
                        schematic versus block diagram            01/01/70 00:00      
                        I have to take exception            01/01/70 00:00      
                           gates            01/01/70 00:00      
                  Not quite            01/01/70 00:00      
               wow talk about out of date....            01/01/70 00:00      
                  Not so fast, there, Pilgrim ...            01/01/70 00:00      
                     various ways to do that            01/01/70 00:00      
                        I'm not sure that applies ... Jez            01/01/70 00:00      
                           Can I suggest            01/01/70 00:00      
                              Thanks for the "spiritual guidance" ...            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                    It's about readability            01/01/70 00:00      
                                       readability            01/01/70 00:00      
                                          also re: readability            01/01/70 00:00      
                                       re: readability            01/01/70 00:00      
                                       type conversion is a pain            01/01/70 00:00      
                                          Yes it's a pain, and it's not well explained.            01/01/70 00:00      
                                             bzzzzzzzzzzzt!            01/01/70 00:00      
                                                Its all about the doc            01/01/70 00:00      
                                                   why the different types?            01/01/70 00:00      
                                                      This is good stuff!            01/01/70 00:00      
                                                         obscurity            01/01/70 00:00      
                                                            Nearly every package has a manual            01/01/70 00:00      
                                                               buffer mode ports            01/01/70 00:00      
                                                                  buried macrocells too            01/01/70 00:00      
                                                                     experts            01/01/70 00:00      
                                                                        Yes, it's about the "experts."            01/01/70 00:00      
                                                   endianity            01/01/70 00:00      
                                                      endianity drives me to insanity ...            01/01/70 00:00      
                                                         HDL wins            01/01/70 00:00      
                     no....            01/01/70 00:00      
                  An interesting dichotomy...            01/01/70 00:00      
                     I don\'t follow ...            01/01/70 00:00      
                        Oy            01/01/70 00:00      
      not synthesizing correctly            01/01/70 00:00      

Back to Subject List