To some extent Richard is right when he says that schematics are useful when you want to show how a system works, the real problem comes when you get designs which are partly schematics and partly VHDL or verilog, then they get really hard to maintain.

Currently the largest design we use has the equivalent of 1.7 million gates of logic all coded as vhdl but I can still draw a top level schematic of the design when I want to talk to someone about how it all works or proposed changes.

Moore and Mealy state machines do have practical differences which make them useful in different applications, rather than being simply academic.
The reason I know that the synthesis is wrong is by following the logic thought the rtl viewer built into ISE and it was possible to see that a state where a register should have been latched had simply not been synthesised.