| ??? 06/25/08 17:59 Read: times |
#156208 - experts Responding to: ???'s previous message |
Richard Erlacher said:
I'm also unhappy about the fact that "experts" never seem to agree on what a set of code means, which makes VHDL difficult and costly to review. WHAT? That statement is weapons-grade stupid. It proves only that your exposure to actual real-world HDL design is minimal. Look, there's a shit-ton of bad HDL out there, and not a small amount of it is promulgated by Xilinx as a "reference design," but STOP BLAMING THE LANGUAGE FOR THE FAILURES OF THE USERS. Please. Just Stop. Andy said:
Richard said:
And none of the three you mentioned did any sort of real logic minimization; you had to break out the K-maps and do it yourself. Palasm, which I used most, made a pretty good attempt at it. I believe ABEL did, too. An "attempt" is nowhere near what was needed. And that's why real HDLs like Verilog and VHDL came to the fore, and the others remain for legacy design using PALs. Cypress managed to make BUFFER mode work just fine with buried macrocells. Yeah, for their very specific and very limited version of the language, and a very specific and very limited target device set. I used Buffer mode when programming the CY37C256 that was on the board included in their EVK for that series of CPLD's. I think the difference is that they (Cypress) never built FPGA's. There must be some reason it's unpalatable to synthesis tools for FPGA, and so they dropped it. Which I enumerated, and which you ignored. I am done banging my head against your intransigence. Don't worry, be happy with schematics. And good luck doing a non-trivial design in them. -a |
