There are several ways of performing type conversions in VHDL, but what I'm after is something that won't illicit a response of, "Hey, what's this???" which is what I get when they see
...
IF (COUNT = SLV_CONST (84336, 17))
...
If someone could suggest a way of doing the equivalent where it doesn't fall in the middle of the "meat" of a process that otherwise would be fully transparent, I'd be really interested.

I make no claim about proficiency in VHDL, as I've been fiddling with it primarily to generate testbenches, which for which it does quite well.

There are many encoder/decoder functions, particularly combinatorial ones, that are very easy and concise in VHDL, as opposed to lotsa-gates on a drawing. For those I prefer to generate a symbol to put in a higher-level block diagram, so people don't have to look at lots and lots of pages of listing and subsequently guess at how the whole thing fits together. It's cheating, I know, but it allows me to get the job done, quickly, smoothly, and easily. There are some rough edges, because I'm not very good with VHDL.

However, because we used schematics for about 100 years before there were HDL's, lots of us old-timers can work very well with 'em. One requirement, of course, is that they have to be intelligently drawn. Folks who've been looking at schematics for 50+ years recognize how that's done. I don't suppose it's taught any longer. It really wasn't taught when I was in school. You either knew how, or you listened to the complaints of those who did. Eventually, you learned.

Until 1980 or so, there wasn't much interest in HDL's, as there wasn't much programmable logic. There certainly wasn't software comparable with what's in use today.

Actually, I've spent quite a lot of time doing what I needed to do with VHDL, and this business with type conversion has often been a pain.

In the example you provided, Andy, there's no output other than TERMCNT. If, however, you wanted the count bits as output, a different approach would be needed, and that would entail a type conversion. What I find frustrating is that I've so far been unable to find a thorough description of how that should be done. As with most things in VHDL, I'm sure there are numerous ways.

BTW, does that count process work without rst in the sensitivity list?

RE