| ??? 06/23/08 05:33 Read: times |
#156114 - HDL wins Responding to: ???'s previous message |
Richard Erlacher said:
I first ran into this problem a couple of years back when I was conjuring up a SERDES/modulator block for a comm link. When you left-shift data coming in to a SIPO register as bytes/words, whatever, the lsb is sent first, as the leftmost bit, and, since the XILINX libraries don't have right-shift registers ... well, I got used to that. Of course, if you're using an HDL, changing things like shift direction and which bit goes first is pretty trivial. In fact, I just revamped my SPI master module to include all four configurations of an SPI master, modeled after what SiLabs does, and I added bit direction (left or right shift) and MSB- or LSB-first options. Set a handful of generics and voila, a completely-configurable SPI master (no arbitration and such though). I even added an option that determines if an SPI receiver is built or not. Very handy. Now, if you're doing your comm's using a packet in the form of a bit-vector of length, say, 1500. So, you have that long a bit vector and the first bit you "see" is the leftmost bit. However, if you specify that bit vector in HEX rather than in binary, which bit is the lsb? The LSb is ALWAYS the right-most bit. It may be called bit 0 (like normal) or bit 31 (like PPC) but it is always the right-most bit. Now I'm about to fiddle with a MIPS problem ... how does it arrange its bits/bytes/words/long words ... ... RTFDS. -a |
