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???
06/19/08 02:05
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#156025 - no....
Responding to: ???'s previous message
Richard Erlacher said:

HDL's are popular with coders because they don't have to get their hands dirty, and don't have to commit themselves to anything they can't edit away. They are pretty good for expresing some functions, e.g. a binary to 7-segment encoder, which takes a 'B' size schematic if you draw out all the gates, yet it fits on half a page of VHDL. There are MANY other such functions, but there are also some that are very easily and clearly expressed in schematic diagrams.


That is NOT the reason HDL's are popular. As I said, HDLs are popular because you simply cannot manage any reasonably sized project with schematics. They're too slow to draw and much more difficult to verify.

HDL on the other hand is fast to implement and verify. What are you talking about "dirty hands"??? You're designing the exact same thing...one with a schematic and one with HDL. Your hands will be equally "dirty" no matter which tool you use. That's simply an invalid argument.

Give me one example of something that is difficult to describe using HDL, but easy in a schematic. What real engineer is implementing a 7 segment encoder and calling it a day????? That's one extremely small part of some HUGE design. Who cares about something so simple?? Like I said, show me the schematic for the pipeline of a pentium 4. If it were the right tool people would use it. It's just not the right tool anymore. There is no reason at all not to be using HDL.

Also, tell me how you're doing to do a behavioral simulation of your schematic? Does your standard cell library have schematic symbols with FO4, timing info, etc, etc?? I doubt it!

By the way - even if you DID use schematics they'd still be compiled down by your CAD tools to.....HDL!!! I'm not sure that you can even make a schematic in design compiler...

List of 51 messages in thread
TopicAuthorDate
xilinx ISE 10.1 is broken            01/01/70 00:00      
   a lot of their stuff has been broken lately ...            01/01/70 00:00      
   broken!            01/01/70 00:00      
      JSM            01/01/70 00:00      
   ah ha well.....            01/01/70 00:00      
      v7 was a stab at a rewrite, as was v8            01/01/70 00:00      
         Schematic?            01/01/70 00:00      
            Once upon a time ...            01/01/70 00:00      
               jesus            01/01/70 00:00      
                  it's not the technology ...            01/01/70 00:00      
                     kind of            01/01/70 00:00      
                        Is the synthesis really wrong, or just the RTL?            01/01/70 00:00      
                           nope            01/01/70 00:00      
                              Thanks            01/01/70 00:00      
                                 Anyway            01/01/70 00:00      
                        schematic versus block diagram            01/01/70 00:00      
                        I have to take exception            01/01/70 00:00      
                           gates            01/01/70 00:00      
                  Not quite            01/01/70 00:00      
               wow talk about out of date....            01/01/70 00:00      
                  Not so fast, there, Pilgrim ...            01/01/70 00:00      
                     various ways to do that            01/01/70 00:00      
                        I'm not sure that applies ... Jez            01/01/70 00:00      
                           Can I suggest            01/01/70 00:00      
                              Thanks for the "spiritual guidance" ...            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                 decimal            01/01/70 00:00      
                                    It's about readability            01/01/70 00:00      
                                       readability            01/01/70 00:00      
                                          also re: readability            01/01/70 00:00      
                                       re: readability            01/01/70 00:00      
                                       type conversion is a pain            01/01/70 00:00      
                                          Yes it's a pain, and it's not well explained.            01/01/70 00:00      
                                             bzzzzzzzzzzzt!            01/01/70 00:00      
                                                Its all about the doc            01/01/70 00:00      
                                                   why the different types?            01/01/70 00:00      
                                                      This is good stuff!            01/01/70 00:00      
                                                         obscurity            01/01/70 00:00      
                                                            Nearly every package has a manual            01/01/70 00:00      
                                                               buffer mode ports            01/01/70 00:00      
                                                                  buried macrocells too            01/01/70 00:00      
                                                                     experts            01/01/70 00:00      
                                                                        Yes, it's about the "experts."            01/01/70 00:00      
                                                   endianity            01/01/70 00:00      
                                                      endianity drives me to insanity ...            01/01/70 00:00      
                                                         HDL wins            01/01/70 00:00      
                     no....            01/01/70 00:00      
                  An interesting dichotomy...            01/01/70 00:00      
                     I don\'t follow ...            01/01/70 00:00      
                        Oy            01/01/70 00:00      
      not synthesizing correctly            01/01/70 00:00      

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