| ??? 06/25/08 03:42 Read: times |
#156179 - buried macrocells too Responding to: ???'s previous message |
Andy Peters said:
I guess I'll shortcut this by saying, "stop complaining about HDLs and start using them." I didn't learn all of this stuff overnight, nor do I expect you to do so. But the more you complain, the less you learn, and the less willing anyone will be to help you. My gripes have been about the documentation, not the language. I'm also unhappy about the fact that "experts" never seem to agree on what a set of code means, which makes VHDL difficult and costly to review. BTW, I was using HDL's, (ABEL, PALASM, CUPL) in the mid-80's. That hasn't helped a bit with VHDL. Of course not, in much the same was as knowing assembly language won't help you program in Ada. CUPL was a buggy nightmare. Indeed, it was! ... and still is. And none of the three you mentioned did any sort of real logic minimization; you had to break out the K-maps and do it yourself. Palasm, which I used most, made a pretty good attempt at it. I believe ABEL did, too. Also, I totally fail to understand why the BUFFER mode has seemingly fallen by the wayside. It precisely corresponds with macrocells in CPLD's, in that it's a macrocell with feedback. It would make sequential logic a lot more readable in VHDL. Actually, there's an excellent explanation of this in Ch 21 of Ashenden, 2nd Edition, page 616. He gives four good reasons, the third and fourth being the most damning: A buffer port can only have one source, meaning it can't have multiple drivers, meaning that the port can not be used for a tristate output. A buffer port cannot be used as one of a number of contributors to a resolved signal. This means that you can't do tristate or wire-or or wire-and logic. While you might think it "precisely corresponds with macrocells in CPLDs," that's only useful if the macrocells are at the I/O pins. Cypress managed to make BUFFER mode work just fine with buried macrocells. There is discussion that "readable" OUT ports might be introduced in the next update to the VHDL spec, if only to satisfy the Verilog folks who are forced to use VHDL for a project.
-a I used Buffer mode when programming the CY37C256 that was on the board included in their EVK for that series of CPLD's. I think the difference is that they (Cypress) never built FPGA's. There must be some reason it's unpalatable to synthesis tools for FPGA, and so they dropped it. RE |
