Any numbskull can figure out a simple schematic if it's drawn properly. In a hierarchy, blocks on the higher levels are represented by schematic sheets on a lower level. If you know what a 74163 is, you don't need to look at its schematic. If you don't, well you'd best look. It's no different with construction drawings. If you look at one that's well prepared, it will have details where details are necessary, but you'll get the "big picture" right away and can examine details as needed. If it's badly prepared, well, all bets are off.

However, an HDL is purported to be standardized. Schematics were not. It's the same way with other drawing packages. The incompatibility of various packages is the product of software design and not of the character of schematics, or of graphic design in any other arena.


XILINX even published a manual for ECS, but it was never in synchronization with the product they shipped. Altera's package worked as well, but their manual wasn't any better. When the manual for ISE v5 was published, they were already on ISE v7, which, BTW, didn't have a useable schematic package. Few schematic package manuals are as poor as the one XILINX provided. Not even bEagle is that lacking in critical detail.

Nearly every serious schematic capture package has a manual with a chapter on hierarchical organization of schematics.

There's nothing mysterious about schematic hierarchies. Proper drafting is the key. It's like developing legible handwriting. Most people don't develop it until well after their most important work is already written. They do eventually appreciate it, though.

The reasons there are different schematic formats is because every schematic format originated in a commercial product. There has never been a standard for schematic diagrams before the Mil-Std-whatever it is, and most folks who created software didn't like the military very much, so they avoided military standards. They did use the Mil-Std symbols for a couple of decades, though. The ANSI symbols were a flop, though TI did give 'em the benefit of the doubt and use them in their later databooks. The reason the formats were originally different is like the reason Verliog is different from VHDL. They're different products, and, of course, for commercial reasons, the vendors prefer that you not be able to use a competitor's product's output as input to theirs. They want you to be "locked in" to theirs.

With schematics, there is still no standard, and, there's seldom a way to transport a schematic from one vendor's product to another.

In general, it's pretty tricky transferring content from one graphic package to another. The EDA software vendors have taken pains to make it difficult to move from one vendor to another. I don't know whether that's by design or just the result of chaos. It does look like chaos, in either case, though.

BTW, I was using HDL's, (ABEL, PALASM, CUPL) in the mid-80's. That hasn't helped a bit with VHDL. Also, I totally fail to understand why the BUFFER mode has seemingly fallen by the wayside. It precisely corresponds with macrocells in CPLD's, in that it's a macrocell with feedback. It would make sequential logic a lot more readable in VHDL.

RE