I've forgotten the differences between Mealy and Moore and whatever state machines, because those differences are really academic.

I always write my state machines as a single clocked process. The dual- (and triple-!) process versions are unmaintainable recipes for disaster. They're used only in examples, never in real-world apps.

Anyways, sometimes state machine failures occur when its inputs are not synchronized to the state machine's clock.

Also make sure that your state machine has a proper reset and proper reset state. If using Verilog, enforce the "full-parallel" option. I always tell the synthesizer to build "safe" machines.

-a