Jez,
Back when I was using ARM CPU's, each and every one, even the ones from ATMEL (which didn't work) had PLL's for purposes of generating their internal clocks.

Unfortumatenly the type of PLL used to generate their internal clocks are not the type I'm interested in using. All that's needed for what I want is an effective DPLL that captures within <15 clocks, acquires over .05%, and tracks over 3% or a phase-detector, error-amplifier, charge-pump combination that does the same. The latter will be heavily dependent on external passives and their configuration, so I prefer the former.

These ARM's all contained ethernet MAC's, and at least one or two of them had incorporated PHY's on board. Each PHY has a DPLL of the type I'd want. Clearly this is implementable. If one wishes to support high-speed serial communication over a switched network or modulated carrier, where slight differences in phase and frequency have to be accomodated, one has to have the means with which to synchronize with the incoming signal. The PLL used to generate the system clock also offers potential benefit in that it will allow precise synchonization with an external signal. The reason this would be of interest to small MCU users is that it would enable the code being executed to be precisely synchronized to an external process, thereby ensuring that no on-the-fly resynchronization during the task need be processed.

RE