there is no other asnwer. It is totally application dependent

I am designing new 8051 derivatives
Do introduce what you end up with when it is done.

if you are talking about CODE flash, the answer is 64k, anything more will be putting a dog in front of an oxcart.

However, if you are fiddeling with code memory schemes, consider, instead of bank switching a chameleon. This would be a very nice chip if you had to design a product that had to be backwards compatible. What I mean is a chip with (I could use 2, some may want more) code spaces and the code initially started would detect "something"and if it was the 'old' type totally switch to another 'memory page' and run as if what is in that page is ALL code WITHOUT ANY overhead after the switching.

And, would the presence of an extra SRF register (in an unused address) for bank switching create problems be likely to create problems with existing code?
CODE Bank switching, in my opinion, means you have chosen the wrong processor, DATA bank switching is another matter. For SFR based CODE bank switching, have a look at the SILabs f12x, it is right there.

I have done (well not, as I were about to say, thousands) many '51 designs ranging from the simplest to the most complex and have, in many cases had to use data beyond 64k, but never code beyond that.

Of course, if you decide to 'forget' which processor you are using and install a RTOS, do not know how to write code that 'fit' the '51 etc, you may have to resort to bank switching, but I would never make that a concern in "designing a chip"

FYI I have a product with 64kbyte (more than ample) CODE flash and 2 mbyte DATA flash.

DO NOT forget to include JTAG (or some other form) ICE functionality. A chip you cn not ICE is only worth the trashbin.

Erik