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???
10/20/06 19:50
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 		 #126834 - Flash Reliability
Responding to: ???'s previous message
Thanks for the feedback.

By using a separate flash chip, I get a better reliability than by using an embedded flash chip within the same die. Logic and Flash processes are different, and it is always a compromise to mix the two on the same die.

I am talking about 1,000,000 write cycles and 20 year data retention, and you generally can't get those numbers in a hybrid process.

I'll research the Flash reset issues. I don't know enough about them. My first thought is that as long as the power remains supplied, the flash chip will continue doing whatever it is trying to do (write, erase, etc) even though the processor has been reset.

List of 59 messages in thread
TopicAuthorDate
How much flash should an 8051 have?            01/01/70 00:00      
   enough            01/01/70 00:00      
      Code Flash VS Data Flash            01/01/70 00:00      
         hints            01/01/70 00:00      
            Max Clock Speed, Etc.            01/01/70 00:00      
               that\'s a cop-out            01/01/70 00:00      
                  Not a cop-out            01/01/70 00:00      
                     can you sell it for less than $1.41            01/01/70 00:00      
                        Replacement costs            01/01/70 00:00      
                           then please stop arguing one point from the perspe            01/01/70 00:00      
                              The replacement market            01/01/70 00:00      
                                 How will that help?            01/01/70 00:00      
                                    Flash Reliability            01/01/70 00:00      
                                       not really - look out            01/01/70 00:00      
                                          More on Flash Reliability            01/01/70 00:00      
                                             XRAM replacement            01/01/70 00:00      
                                                Write-While-Fetch            01/01/70 00:00      
                                    That does not appear to be the target.            01/01/70 00:00      
                                       6/12 Clock Mode and XDATA support            01/01/70 00:00      
                     Have you looked at the one-clockers?            01/01/70 00:00      
                        How do you propose to fit that in the instruction            01/01/70 00:00      
                           map registers            01/01/70 00:00      
               clock speed            01/01/70 00:00      
                  Not a bad idea ... that's what Dallas did!            01/01/70 00:00      
                     Clock Speed Reduction            01/01/70 00:00      
                        if you knew the chip            01/01/70 00:00      
                           actually, it does either speed up or slow-down            01/01/70 00:00      
                              Variable clock speed            01/01/70 00:00      
                                 clock vs power            01/01/70 00:00      
                                    SIngle clock power            01/01/70 00:00      
               when i did this            01/01/70 00:00      
                  0.35u process & 64K            01/01/70 00:00      
         Big Flash - coda and data!            01/01/70 00:00      
            Does Zylogic = Triscend?            01/01/70 00:00      
               Zylogic; Triscend            01/01/70 00:00      
            that should make it clear            01/01/70 00:00      
         Data Apps            01/01/70 00:00      
   bank switching mechanism (RFC)            01/01/70 00:00      
      Bank Switching            01/01/70 00:00      
         that's how it's done traditionally ...            01/01/70 00:00      
         Keil support            01/01/70 00:00      
      bank switching no0t needed            01/01/70 00:00      
         "bank switching no0t needed"            01/01/70 00:00      
            if you read it all            01/01/70 00:00      
               I'd even tend to believe...            01/01/70 00:00      
      No lock IRQ            01/01/70 00:00      
   Parkinson's Law...            01/01/70 00:00      
   The trouble with PLLs            01/01/70 00:00      
      nearly every ARM has a PLL            01/01/70 00:00      
   yeah i understand that            01/01/70 00:00      
      ethernet mac            01/01/70 00:00      
   Dougal was..            01/01/70 00:00      
      Sorry to hear about your misfortune            01/01/70 00:00      
   no not seriously            01/01/70 00:00      
      I don't think he hates you, Jez            01/01/70 00:00      
      That must be the most painful            01/01/70 00:00      
         it's not a killer, but you do notice it            01/01/70 00:00      
   well jasmine can ride him all day            01/01/70 00:00      
   Gives a new meaning to that old interview question            01/01/70 00:00      

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