I was specifically thinking about the idea of running the chip slower to decrease power in my earlier comment. We have a fully synchronous, one-clock design that is good for modern ASIC / FPGA synthesis and implementation, but definitely draws more power than the gated clock approach used in the original 8051 design. Idle stops half of the clocks, but a variable divide-by-n on the clock in an interesting approach to power reduction while still being active.

My gate arrays support internal PLLs and DLLs. so making a 2X or 4X speedup is not difficult.