Hi Jan:

I am guilty of using design terms rather than 8051 terms.

A single clock per instruction CPU will draw less power than the 6/12 approach.

However, designing with a single, synchronous global clock tends to use more power than using multiple, local clocks. For example, I can write data into a SFR register either by using the write strobe to clock a latch (multiple clocks) or by always clocking a register with the global clock, and using the write signal to force the data into the inputs of the register where it is loaded on the next clock.