What I pointed out was that when you write to the i8255, the data is "out there" now, i.e. within a cycle. With the serialized methods, e.g IIC, it has some latency.
that is why I listed
1) use a micro with sufficient internal Flash and RAM
2) use an 8 port micro
3) a small el cheapo slave processor
7) parallel latches (output)
8) gates in parallel configuration (input)
9) a WSI chip
10) CPLD/ASIC

If you compare that with any "standard" 805x-core MCU (none of which support IIC, SPI, etc.) it means that you have to bit-bang the IIC/SPI. Just how fast can you do that on a "standard" 805x-core MCU?
AFAIK "a "standard" 805x-core MCU" is a thing of the past with the possible exception of a few super-economy devices (and for those, we should not discuss external logic)

Serial I/O is not the way to talk to code memory
Who friggin' cares, I know of NO derivative that is not about to be discontinued that does not have internal flash.

These ST (formerly WSI) devices look like a possible way, but I doubt they're cheap and ubiquitous, particularly in Asia.
what will be "cheap and ubiquitous" in singles is what the "teaching institutions" use. Thus there need be a revolt among students against teaching what was taught when the teacher was a student and the king of diamonds were a jack GET WITH THE TIMES

It has to be answered in the context of "I have three days and little money."
A couple of HC chips which can do the same so much better than the antique will cost far less

Erik