How the device processes the clock is of little concern so long as one knows the cycle length, particularly the length from falling-edge ALE to when data-out is valid and to when data-in must be valid. One has to read the datasheet in order to know when the addresses and controls become valid and when the inputs must be valid in order to function properly.

It's difficult to communicate about matters such as this in a forum where many participants have never had to concern themselves with such issues as setup and hold times on addresses and data, /Rd and /Wr pulse widths and the relationship of valid data in/out with respect to each.

A "standard" i8751, which I use as reference because I have one on the bench even as I write this, fully capable of 12 MHz but operating at 11.0592 MHz for the benefit of a monitor program that relies on it, has a specified access window, meaning the time from valid addresses on P0, to the last point in time at which valid data IN must be available at P0, is about 517 ns. Actually, if it's gated with /Rd, it's still on the order of 400 ns, as that's the pulse width of /Rd. That's not very demanding at all! Even the old, slow i8255's can handle that. The write cycle is similarly generous in its timing on a "standard" 12-clocker.

Whether a specific MCU that DOES have the external memory bus available is a 2 clocker or a 6 clocker doesn't matter, so long as one knows the external memory cycle timing parameters. These are just as important with external SSI/MSI hardware as with an i8255 or other LSI.

There's no point in discussing "expansion" of I/O on devices that have no external memory bus for now. While it's possible to do that, it's not the first thing that comes to mind when one asks how to expand the device's I/O, and the obvious way should be handled and presented in a useful format before esoteric approaches to making a device something is wasn't intended to be are discussed.

RE