Well, I've started the design, and now I'm staring at the tools, trying to make sense of it all.

The VHDL for the datapath is complete and the Actel ProASIC architecture seems to work well enough for what I want it to do. Unfortunately it does not have LUT-based shift registers a-la Xilinx SRL16 so I had to recode a small FIFO using flip-flops. It ate up a bunch of logic but I've got enough anyways.

The next step is integrating the processor with the HDL. Basically I just expose a handful of registers mapped to the processor address space.

Actel support through the local FAE has been very good, by the way.

-a