Sorry Richard, once more, my reply was not informative. Let me give you all a detailed reply now, and if you want any more details, I am happy to give.

There are 10 digital pins, out of 48 pins in the Zigbee transceiver. They are:

two control pins: Voltage regulator enable and Reset (no problem, they are working fine as per the datasheet).

four data interface pins: SPI interface: CSn, SCK, SI and SO. I can get the internal status of the pins thru the SPI interface, so these pins are also fine (no need to probe)

four status pins: FIFO, FIFOP, SFD and CCA (these pins are to be probed.


Now, the status pins are generally at logic low, but they change the state as and when a packet is transmitted or received. I have a dev. board from Chipcon, which could act as a node, and I have interfaced a stand-alone 2420 module and mega8535, which is the another node. My current interest is to set up the firmware and driver for the 2420 chip. (the AVR used is not for any specific purpose, I can get hardware SPI, since 89s8252 is difficult to find).

The status pins behave as follows: (while receiving a packet)

SFD: When a packet is received, and when the Start of Frame Delimiter is Valid, this pin goes high, and stays high until the packet is completely received. So, the approx. time for which the SFD pin would be high is more than 100usec.

FIFO: This pin goes high when a new byte arrives in the internal data buffer. This happens only after the SFD pin going high, because, then only a packet can be received.

FIFOP: This pin goes high when the internal buffer overflows after a defined limit. This pin will also change only after SFD pin changes.

CCA: Clear Channel Assesment pin, is not needed now, since this data can alternatively be got over the SPI interface.

Richard said:

Under precisely what conditions do you want to sample those signals?

I can give a command over SPI to enable the reception of packets. Then the chip will respond to packets, and the status can be received over the status pins. I would like to monitor the pins before and after turning on the reception.

Pre-trigger time: 100-300usec is enough

Post-trigger time: Until the SFD goes low(until a single packet is completely received or rejected)

Approx time duration, 300usec (pre trigger) + ~1000usec(post trigger), and the trigger being the SFD pin going high (reception of a packet).

(Forgive me, but I'm unfamiliar with this particular part, so those signals don't mean much to me.)

I am sorry for my incomplete reply, dear Richard. Since this CC2420 is fairly a new device, I cant find many users and materials in the internet. And the signals are really mysterious for me!

Whatever the packet I send, my board receives only first 3 bytes of any packet, then nothing. I have tried all possible combinations of initial settings, and so on, but dint find a clue yet. Even the technical support people give the datasheet reference as answers to my questions. There are two mysterious registers within CC2420, which are not well documented in the datasheet, and, hardly anyone knows what they are for.

May be the clue is in these status pins, so the Logic Analyser post here.

Thank you all for your valuable posts and comments here. I am getting highly useful data, which are, by no means, I would have learnt.

Warm Regards,
Vignesh