Well ... logic analyzers are popular topics. The guys who don't have one want to build one, and the guys who have one want to build a better one. Go figure!

What VIGNESH probably ought to do, IMHO, is wire up a couple of 8-bit counters, e.g. HC269's, and address a (where is that %$#@! thing ... I've got one right here ... Oh, here it is...) UM61512 or the like as a buffer ram. Then he attaches his signals to that, up to 8 of 'em, and (1) uses a dip-switch and a 74HC68x-series comparator to detect the trigger state (one-level) (uses two HC574's to capture the address when the trigger occurs, (3) adds 0x8000 to the count so he always has 32 KB of storage after he triggers, and lets it run until the count+0x8000 either overflows. To that he adds an MCU that can move the data into his PC for display and processing. Now he has a device that can sample 64K times into a buffer that will place his trigger in the middle so he has lots of history. He can also see quite a bit of what happens afterward. There's a little more to it than that, but you get the idea.

Once this is all in order, which is no small accomplishment, he has a tool that can sample up to 8 signals at about 50-80 MHz. If he puts on a 74HC4046 PLL, he can synchronize the sampling with a multiple of the SUT (system under test) system clock so he doesn't have that ugly frame slip that looks so bad on an asynchronous-sampling logic analyzer. It's not perfect, BTW, but it will do useful work. He still needs a good oscilloscope, though.

RE