Jan, got a link?

I've got a design for an FPGA-based logic analyzer kicking around in my notebook. It's 16 levels of pattern/edge triggering (fits in the FPGA SRL16) times however many bits. Think: HP1660. I've got a bunch of Verilog written and simulated, so it should all work. One concept is to use the DDR inputs on the FPGA. Without them, though, I suspect I can get 150 MHz I/O, which is almost fast enough. External SRAM provides sample storage. The sample storage itself is essentially a big circular buffer. Think it through; it's actually kinda simple. It's always saving samples to memorye (and incrementing the memory pointer); when the trigger logic fires, it simply stores the current memory pointer and continues sampling until the buffer is full (when it wraps to the saved pointer minus 1). Then sampling stops and the data are transferred to the host.

Silicon Labs has the new '340 chip which has the external memory interface so interfacing it to the FPGA is easy, and I can do either USB or serial from it. It's full-speed (12 Mbps) USB only, but I don't think it'll be too slow transferring 4 MB sample data.

The hardest thing is writing a useful host (PC or Mac OS X) program! I was thinking that I can send the data over in VCD (Verilog change dump) format and parse it and display waveforms using GTKWave, and a little custom program sets up triggers and so forth. But last week I was poking through LabView and there's a LabView control that does exactly what I want, so I may go that route.

-a