| ??? 03/07/06 09:03 Read: times |
#111483 - architecture Responding to: ???'s previous message |
Richard Erlacher said:
In order to sample a digital waveform of 1 MHz frequency, one has to sample at a minimum of 2 MHz. Within that half-microsecond interval, a microcontroller has to fetch the data, put it somewhere, increment the pointer to where he puts it, check to see whether he's done yet, then go back and do it all again. In AVRs, the basic sample-and-store cycle is as much as IN R16,PINA ST Z+,PINAwhere the autoincrement of the "pointer" register pair takes care of the third required operation. Similar can be achieved on those '51 clones which have DPTR autoincrement, where the cycle would shrink to mov a,P2 movx @dptr,a ;autoincrement mode set previously. Unrolling the cycle, we get rid of the counting and endcheck - simply repeating this pattern as many times as much samples we want to take (as much internal SRAM is available). This sounds as a terrible waste of code memory, but in fact this comes in huge amounts very cheap - we need like 4 times as much as SRAM we have, so that's 32kB of FLASH for 8kB of SRAM, so it will fit nicely into ATMega128 or similar. At a 16MHz clock, this scheme yealds sample rate above 5MHz (IN is 1 cycle and ST is 2). Of course, delayed trigger is impossible using this scheme but for many applications it does not really matter. I believe, 2MHz sampling is still achievable even with delayed trigger, or with sampling based on state changes (storing timestamps). And - anyway, I still don't know what is the ultimate sampling frequency needed for the ZigBee module, so all this is only a hypothetical discussion. Jan Waclawek |
