..then probably I have to take the other way! Thanks for your replies, dear Richard and Jan. I have decided to roll a Logic Analyser(LA) for myself, with a separate MCU getting the inputs (an 8 bit port) and sending them to PC thru RS232, along with some line drawings using Borland C.

Ofcourse this is only a 'quick fix up', but I might later come up with FPGA or USB based solution.

By the way, Richard, I also have access to Xilinx CPLD dev. boards(XC9.. series I reckon) in my institution, but pretty old by themselves, I have to go for something fresh regarding VHDL implementation of the LA.

The thing which I was worrying for a long time is, as we have direct control the timing issues of microcontrollers, we could precisely tell when to sample, and when not to. But on the PC side, its somewhat difficult.

I had once written a TSR for the clock interrupt, which was ticking at 18 times per second. But I really dont know how long does it take for the TSR to run, and so on.

Even if I do precise timing in the MCU side, I cant(and dont know hot to) assure the time axis in the PC side. This is the major reason which had kept me busy with other projects, not concentrating on LA. I have to come up with a solution today, Sunday!!

Cheers,
Vignesh