This kind of puts me in mind of a design I was working on for steve which kind of went a bit tits up but basically if you have an input vector of the inputs you are interested in and a high speed counter you can use a fifo in your FPGA to log changes in the input vector and the fifo simply records the timestamp generated by the counter and the new vector value.The fifo can then be read from the pc side at regular intevals.Which is a rather simplified version of a standard logic analyser,obviously in commercial versions the fifo is implemented in gallium arsenide based ASICs so you can have stupidly fast events.The trick is to implement a large enough counter which can be clocked at high enough clock rates and of course the logic to detect changes in the input vector and use that to trigger a new fifo entry.32 bit counter running at 100 Mhz is do-able using a xilinx spartan 3 and I have a suitable fifo package if you are interested.The fifo probably has to be asyncronous which is always good for a laugh but there are very cunning tricks you can use to avoid the usual problems with async fifos