One of the problems with this RC reset circuit, derived from a very old Intel application drawing, one in which there was little effort toward timing the reset pulse width, is that it was designed to ensure the pulse was "at least plenty" long enough.

Erik has pointed out that this approach to resetting the MCU does nothing useful when the Vcc level momentarily droops to somewhat below the tolerable lower limit on Vcc. Totally passive approaches to solving this problem get to be too power-consuming and, for most people, too time-consuming for a problem so easily dealt-with with a supervisor IC. Very many "issues" with the reset timing have "gone away", once a supervisor IC has been introduced, though little study has been devoted to finding the source of the trouble, such that most people have concluded, perhaps correctly, that the problem was with reset. One can't continuously argue against such results, though there's no proof that the problems begin and end with the reset circuit.

Clearly, however, RESET, pulled down with an 8.2 k-Ohm resistor, and held up with a 10 uF cap, is not the "be-all and end-all".

One significant issue, however, is the decay of Vcc once power is turned off. I've observed some MCU's continuing to run during slowly decaying Vcc, despite active RESET during slowly decaying Vcc. This suggests a number of things, many of which can be dealt-with by means of a supervisor IC. I rather prefer to introduce a rapid discharge of the Vcc-to-Gnd capacitance on the board. Some supervisor IC's, with the aid of an external transistor or two, can support this. Though I've experimented extensively with this problem, I can't yet provide direct evidence to support the notion that this is necessary.

RE