Sorry, but that suggestion sounds like a design a first-year CS student may suggest.

It is 100% impossible to guarantee that you can run two processors in lock-step. It is enough that one of them receives an extra interrupt - either from a non-shared pin or because of noise - for them to diverge.

Any protocol used to send data concurrently to multiple listeners must be designed in a way that the multiple listeners can perform the required synchornization on their own which will require that the timescale involved for synchronization is way different than the timescale used for the instruction processing.

The protocol should define sufficient time between each message that an addressed slave may consider if it should acknowledge, ignore or reject a message. And the protocol should make sure that if a message is sent to multiple listeners, then the listeners should use an address identifier or similar to send the acknowledges in sequence. Or there should be some other form of acknowledge - for example sharing an open-collector output where the slaves may vote ok/error.

But in no way should a design require the slaves to run in lock-step on a cycle-by-cycle basis.