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???
08/12/09 11:22
Modified:
  08/12/09 11:58
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 		 #168337 - multiple chips ....
Responding to: ???'s previous message
I,am working with Aduc812 from Phytec.
does that have to be? if no dual UART or HW IIC/SPI it is not very well suited for multiprocessor apps.

it is an good idea using UART, but i have two slaves, so how could i say them both to start by UART?

multiple chips can be implemented VERY painfully OR in a relatively simple way.

the difference is master and slave(s) is relatively simple anything else requires a bottle of aspirin.

Why not just connect a master to the PC and let that communicate (I recommed via hardware IIC) with the rest?

Erik

EDIT: you may get by with a MASTER w/o HW IIC/SPI, but SW IIC/SPI for SLAVES is a true aspirin salesman

List of 71 messages in thread
TopicAuthorDate
Communication between two 8051            01/01/70 00:00      
   I'm going to recommend            01/01/70 00:00      
      I'm going to recommend            01/01/70 00:00      
   I'd recommend ...            01/01/70 00:00      
      irrelevant, however            01/01/70 00:00      
      chip            01/01/70 00:00      
         multiple chips ....            01/01/70 00:00      
            Perhaps you don't need two UARTs            01/01/70 00:00      
   Side note, multiple COM ports            01/01/70 00:00      
      FTDI Multi-UART to USB            01/01/70 00:00      
   Clarify?            01/01/70 00:00      
   Parallel 8051 TXs and RXs            01/01/70 00:00      
      Two transmitters            01/01/70 00:00      
         Which lesson to give?            01/01/70 00:00      
            and ..            01/01/70 00:00      
            Like good little children            01/01/70 00:00      
            Jimmy Neutron/Phineas & Ferb            01/01/70 00:00      
            Tony Gelonese's method should work...            01/01/70 00:00      
               no, and yes            01/01/70 00:00      
         some more thought...Per Westermark            01/01/70 00:00      
            It is all in the subpressed details            01/01/70 00:00      
               SIlabs chips would burn            01/01/70 00:00      
      No, That won't "just work"            01/01/70 00:00      
         I think there's more to this than meets the eye            01/01/70 00:00      
            Not always interrupt response instantly            01/01/70 00:00      
               Since the O/P hasn't been back ...            01/01/70 00:00      
                  serial communication            01/01/70 00:00      
                     you are aware?            01/01/70 00:00      
                        You are also aware?            01/01/70 00:00      
                     Synchronize transfers            01/01/70 00:00      
                        Connecting two TX outputs            01/01/70 00:00      
                     Unnecessary complication!            01/01/70 00:00      
                        Different name            01/01/70 00:00      
                        Walter and Walter            01/01/70 00:00      
                           Name            01/01/70 00:00      
                              what are you ashamed/afraid/... of            01/01/70 00:00      
                              Walter, Please eschew obfuscation and equivocation            01/01/70 00:00      
                     That Phytec Board has RS485 and I2C and SPI            01/01/70 00:00      
                        summarizing            01/01/70 00:00      
                           to a nail everything looks like a hammer            01/01/70 00:00      
                        actually ... he hasn't said he needs that ...            01/01/70 00:00      
                           Often important information arrives quite late            01/01/70 00:00      
                           Actually, he did!            01/01/70 00:00      
                              It's not complete            01/01/70 00:00      
                                 he's so stingy with information            01/01/70 00:00      
   Some more Thought....            01/01/70 00:00      
      This assumes perfect synchronization            01/01/70 00:00      
      the longest reply ever            01/01/70 00:00      
         Schematic is Incomplete            01/01/70 00:00      
      Missing boundary limits            01/01/70 00:00      
         Use p3.0 and p3.1            01/01/70 00:00      
            huh?            01/01/70 00:00      
            You need to clarify your requirement!            01/01/70 00:00      
            This contradicts an earlier post from you            01/01/70 00:00      
               agree with most, but???            01/01/70 00:00      
                  clock-for-clock send            01/01/70 00:00      
                     Still not clear!            01/01/70 00:00      
                        I think you lost the thread            01/01/70 00:00      
                           If they're to remain in precise synchronization ...            01/01/70 00:00      
                              Ridiculous            01/01/70 00:00      
                                 Come on, Walter!            01/01/70 00:00      
                                 It's routinely done ...            01/01/70 00:00      
                                    Don't relive your past again and again            01/01/70 00:00      
                                       MCU is a component, not a computer system.            01/01/70 00:00      
                                          Tell me more about femtosecond precision            01/01/70 00:00      
                                             not even then            01/01/70 00:00      
                                                Watch out            01/01/70 00:00      
                                                   Some suggestions for low-jitter processor activation            01/01/70 00:00      
                                                That's exactly what it is            01/01/70 00:00      
                  The two slaves must be in the same state            01/01/70 00:00      
            Is this yet another problem?            01/01/70 00:00      

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