... but with one waveform at half the frequency. That should show you the attenuation at full bandwidth. As for the phase shift ... well, have one waveform at 1/10 the frequency of the other. See what that looks like.

Another thing might be to display the same frequency, even if they're lower than the rated bandwidth, at two different duty cycles.

If you use one frequency as the timebase, but divide one by 1 and the other by 10, you'll see some phase shift. You'll have to check your CPLD/FPGA spec's to predict what the actual phase difference should be, but the 'scope will show you some of that and the 'scope-induced error as well.

One other thing you might try is an edge-detector consisting of an XOR2 and a FTC (T-flop with asynchronous clear). The XOR goes in feedback between Q and Clock, where the XOR takes in the external clock and the xor feedback and generates a (Clock-to-Q(FTC) + Tpd(xor))-wide pulse into the clock input of the FTC. The FTC is equivalent to a JK FlipFlop with J and K tied high. A JK flipflop, for those who don't remember, is a D-flop where D gets J*/Q + /K*Q). You'll get to see what the 'scope does with really short pulses, irrespective of the frequency.

That should provide you some amusement.

RE