You'll find that unless you force it not, to any logic compiler will delete strings of gates because they don't actually do anything useful as far as the compiler is concerned, its like saying a==not(not(not(not(not(not(not(b)))))));
So you have to set a flag on those gates saying do not delete, or something similar, and the delay will be astonishingly unpredictable.
There is a technique called Venier timing which will allow you to measure time intervals with arbitrary precision, and it what is used in high end frequency meters/function generators.Also all the cool kids use LFSRs to generate large counters in FPGAs, they don't slow down with size unlike straight binary counters and take a minimal amount of logic.
having spent some time trying to stop logic compilers from removing redundant logic I can tell you its no fun and the results can confuse the place and route tools.