I'm persuaded that the cap sizes popular when people were using TTL or LSTTL are considerably too large and likely to cause problems of their own when used in combination with mostly CMOS logic.

Adding more capacitance between logic power and gnd will increase the rise and fall time of Vcc with respect to Gnd, but won't help much with noise induced from the environment. Small cap's will help somewhat more but won't do the job entirely either.

I'd guess it wouldn't hurt for someone to take a close look at those cap values in the FAQ so they don't mislead newbies. I'd guess the values presented are, generally speaking, and for the technology popular today, an order of magnitude too large. Further, since people are using 0603's and 0402's, size causing increased real estate isn't that big a problem. after all, there are still smaller sizes.

There's more to dealing with supply bypass than just swamping supply input ripple. The ground bounce created by sharp edges on clocks and on signals in general contribute to overall system noise, but what's needed in this particular case is the need for mitigating externally induced noise, since it's a thoroughly "industrial" environment, with large currents moving around outside the control circuit under discussion.

Managing externally imposed noise might be as simple as using a darlington-input Vcc regulator rather than an LDO. Careful Gnd routing would also be important. The circuit in question might even need to be in a Faraday cage.

RE