Well, I did just prove that if you have a sampling rate of 1024 times / full period (which, for 50 Hz would be 20ms /1024 = 19.5us), then two samples 19.5us after each other at the peak can change with at most 1-0.99998 or 0.002 % relative the "DC-level" value. So I then played with 2-logariths since each bit of an ADC represents a factor 2. And if are a full sampling period (19.5us) off from the peak - the error is still so small that you need a 16-bit ADC to have a chance to catch it.

And you have already told us that your ADC is only able to do 8, 10 or 12 bits of resolution.

So it would then be quite obvious that 19.5us sampling rate (1024 samples in a full period) is way faster than needed for a system that only locates the highest and lowest values - the two extremes - to represent the top-to-top value and then approximates an rms value based on that.

Now, you could obviously perform the same computations with 512 samples/period, 256 samples/period or 128 samples/period (or any other sampling speed you may fancy) and see exactly how much the peak voltage can change for one sample interval. If that is much less than the resolution of your ADC, then you obviously can reduce the sampling rate.

Do you see any problem with my way of thought?

We are talking about a sine wave, aren't we?

So we can use a pocket calculator and compute either sine (90+angle) to see how much the voltage drops for a specific angle (representing the angle change between two samples).

Or we can compute the reverse - what angle will give a dip of let's say 1/256 of the peak value. And then compute what sampling rate that would represent.

Don't you agree that the sampling rate is deciding if we will get a measurement close enough to the absolute maxima and the absolute minima of the signal?

And the voltage reference, your signal conditioning and the resolution/precision of the ADC will decide how exact the ADC will then be able to convert that sample into a digital value for your program to then crunch on.