| ??? 03/15/12 23:10 Read: times |
#186712 - think about this for a minute Responding to: ???'s previous message |
Erik Malund said:
I don't think 100 nF is "right" for IC bypass unless in parallel with about 200pF.
fine if ceramic. Additionally, I believe one should avoid too much power-gnd capacitance, as it will cause far too slow a decay of Vcc. here we go again, with a proper supervisor chip that is NOT a problem sure, in some cases the suprevisors reset output need be connected to more than just the uC, (that's why there are supers woth both RST and !RST outputs) but that is SOP. I'm reminded of a couple of friends here in this area who, back in the days of Apple-][ popularity, produced and retailed a real-time-clock board for the Apple-][. This board had a power entry swamping cap of 4.7 uF, and, on one occasion, one of their boards was sold and lost in the mail. They tried out and preset each board before shipping it, and in the case of the lost board, when it came back in the mail, unopened, after 20 days or so, the RTC was still pretty much on the money, meaning that the oscillator had kept on running and the clock/calendar was still counting. I doubt adding the tiny cap's will hurt
today, in many cases, real estate is at a premium The O/P didn't say anything about limitations on real estate, cost, or power. that 4.7 uF at the power entry will keep things smoothed with today's low-power circuits.
not good enough, if you pull, say 20mA each from 3 ports you need a repository at the uC or you will be playing bounce ball. I'm not persuaded that he's likely to do that, nor is it necessary to have a huge reservoir of capacitor-stored charge. What helps most in managing noise, is high-frequency bypass members. They don't have to be large if the supply powering the on-board regulator is hefty and clean. Hefty means big enough, not necessarily HUGE. YES, the 'rules' in the FAQ are not necessarily #1 in all cases, but in no case will they hurt, unless, of course, you do not believe in supervisors etc. Since I've observed peculiar "unspecified" behavior on the part of 805x's during active RESET, while Vcc was decaying, (a) I'm not convinced that supervisors can solve the power-down side of the problem and (b) I'm not sure what a supervisor is supposed to do with components that don't have a RESET pin. I have a few updates to the FAQ, but last I tried it was not updateable (is that a word?) it is one now ... Erik Frankly, I've put those 3-pin parts in a few app's just for good measure, but until someone tells me how to cope with slow decay on Vcc, when various components have different requirements regarding valid levels of Vcc, I'll reserve judgment for now. That 10 uF cap on the old Intel reset app-note has to be just about as dumb as the stupidest thing anyone ever published. A fast rise time on Vcc fixes most of the problems and I've convinced myself, empirically, that a fast fall-time does that too. I once had a circuit with a supervisor that caused my BBRAM used as a program store to "lose its mind" quite frequently under repetitive power cycles, but when the rise and fall of Vcc was limited to < 100 microseconds, the problem went away for over a million iterations over about 1000 hours. One of these days, I'll get that old system out of storage and hook it up to those two 805x circuits and take some LA pictures to show you. That won't prove much beyond that it happens, but it'll be amusing. RE |
