I don't think 100 nF is "right" for IC bypass unless in parallel with about 200pF.
fine if ceramic.

Additionally, I believe one should avoid too much power-gnd capacitance, as it will cause far too slow a decay of Vcc.
here we go again, with a proper supervisor chip that is NOT a problem sure, in some cases the suprevisors reset output need be connected to more than just the uC, (that's why there are supers woth both RST and !RST outputs) but that is SOP.

I doubt adding the tiny cap's will hurt
today, in many cases, real estate is at a premium

that 4.7 uF at the power entry will keep things smoothed with today's low-power circuits.
not good enough, if you pull, say 20mA each from 3 ports you need a repository at the uC or you will be playing bounce ball.

YES, the 'rules' in the FAQ are not necessarily #1 in all cases, but in no case will theu hurt, unless, of course, you do not believe in supervisors etc.

I have a few updates to the FAQ, but last I tried it was not updateasble (is that a word?)

Erik