However, in my own rather cursory testing, over long periods and with a few different MCU's, I found that my BBRAM was clobbered despite the assertion of RESET during Vcc decay, as there was a supervisor in the circuit
now you are jumping to external components in a discussion about internal flash. If, what would be likely, the reset pin is, somehow, connected to the internal flash enable, your 'findings' are totally irrelevant unless you, in your 'findings' connected the supervisor output to your BBRAM.

if you, Erik, are willing to have a discussion, rather than a "food fight", it can be done, in an MCU-specific context, as well as a general one that's applicable to pretty much all 805x-core MCU's, though there will undoubtedly be some exceptions, but I believe it would be appropriate to do it in a separate thread.
who is "food fighting" not me, I am referring to what many others and I have proven works. If an aspitin cures my headache, I do not rush to Google to find out why. You, however come back again and again to your rise/fall time issue where, as previously agreed, zero would make the supervisor unnecessary but anyhing more than an unspecified 'enough' would make it necessary. Thus since 'enough' is unspecified, INSTALL A SUPERVISOR!!!

If you can't grasp that, resort to your "he that do not agree with me is food fighting"

Erik