What I mentioned was the anomalous behavior of the MCU during decay of Vcc while RESET is active . It did, in fact, occur when the supervisor had asserted RESET.
WRONG< DEAD WRONG you say "the MCU" but are talking about a specific MCU (probably Dallas). There is no Guarantee that all MCUs have a properly designed reset circuitry.

I can't get inside the package any better than you can.
I know, then please, tell me how to get 'proof' of the inner workings of the chip

However, It's a bit of a stretch from "lost flash" to "RESET problem" which is what you concluded.
pray explain the 'stretch'
1) flash NEVER lost w/o power cycle
2) flash occasionally lost by power cycle
3) solid reset during power cycle = no lost flash.

I'd guess it's just as likely your problem would have "gone away", mysteriously as that occurred, if you'd reduced the rise and fall times of Vcc, though that's not been tried at your end, has it?
I can, by sheer reasoning, guarantee you that with a fall time of ZERO, absolute zero, the problem would not exist. However the likely tolerance on fall times (Sure you can pay a fortumne for low tolerance decoupling caps) makes it undesirable to base any design on it. another undesirable effect of relying on fall times will be a tendency to skip on decoupling and I would definitely not recommend that.