NXP LPC23xx, LPC17xx and some few more ARM families have managed quite well by just mapping every hardware I/O signal to two different GPIO signals (with the exceptions of a few signals that have special hardware needs such as ADC inputs). Each pin have four alternatives - GPIO or three custom functions. Having (almost) all custom functions on two different external pins also means the ability to multiplex features. For example an UART would double as two UART by multiplexing between two sets of pins - ok as long as the uC is master and knows that there will not be any incomming data from external equipment A when the UART is muxed to external equipment B. And the chip still has support for pin-change interrupts for the majority of pins when used as GPIO making it possible to notice arrival of UART, CAN, SPI, I2C, ... data.

Settling for just two alternative pins should be doable with a quite small number of extra transistors or large quantities of signal routing inside the chips. But you can still manage a extremely high utilisation of all the peripherial functions without getting stuck by two functions colliding with each other. Too many more advanced chips quickly ends up with lots of hw peripherial functionality locked up because of pin collisions with other functionality that you also need.