Erik,

I actually agree with you about experience being a hindrance sometimes.

Here's one that can be baffling. I've done a handful of Xilinx Spartan 3AN designs in the last year, with one Virtex4 design. Now I'm doing a more-complex V4 design and told the layout guy, "You can use any pin that has a _LC or _CC as a differential output but not a differential input because these pins don't have the built-in LVDS termination."

Well, that's the way it is on Spartan 3AN, but that's wrong on V4. V4's "_LC_CC" pins simply don't have differential output drivers. "LC" means "low capacitance" and I guess by eliminating the LVDS output drivers they gain a 1pF improvement in input capacitance, or something. (Oh, and they DO have the built-in 100-ohm LVDS termination.)

So a boatload of LVDS pairs, tuned to matched lengths, had to be reassigned on other pins and rerouted. Yippee!

This is why we never build boards until the FPGA design is done, or at least in a state where all pins and I/O types are well-defined enough to pass through the tools without error or warnings. Especially this board: 14 layers.

-a