Hard to tell about number of clock phases. The current consumption for a given process is mostly the total number of transistor transitions/second. Rippling the data with timed delays, having asynchronous handshakes or running the steps synchronous does not affect the number of transistor transitions in a bigger way. It is just different ways of timing the data.

The timing diagrams on the other hand does indicate that they are rippling - external signals are expressed based on the external clock frequency +/- a fixed number of ns, instead of mentioning a factional clock frequency.

Their power comparison is with the original 8051, where a lot of transistors is constantly toggling without getting antything done. The steps are ticking, but without a pipeline, here are no new instructions there to take advantage of the toggling transistors. The original 8051 also makes dummy code reads where the result is directly thrown away.

Are all Dallas 1-clockers copying the code to SRAM? The link mentions the use of fast NV-SRAM instead of flash. If I look at the datasheet for a DS89C430/DS89C440/DS89C450, the datasheet specifies flash memory.

We are talking about a 33MHz (33ns/clock) chip, and their text does very clearly mention the non-existence of a pipeline.

Having a flash with 33ns access time would produce data at the required speed. But if the access is started after the previous instruction ended, then there would be zero time left for performing the instruction. Having 16ns access time for the memory and no overlap of instructions would only give 16ns for decode, execute, save.

They would either need a code memory way faster than 33ns, or for marketing purposes decide that overlapped load of the next instruction should not be called pipelining.