The one-clocker with which I'm most familiar is the Maxim/Dallas DS 89C4x0 series. Those really seem to be as fast as they claim, namely 1 MIPS/MHz, but using the "standard" I mentioned, namely it's the number of NOP's it can execute.

The cycle timing, relative to the "system clock", however, is quite close to that exhibited by the standard 8051. I haven't noticed any instructions the timing of which, in system clock cycles, don't match the "standard" 805x.

Of course, what interests me in the Maxim/Dallas parts is the way in which the hardware works, namely the DPTR's and their selective auto-increment/decrement features, the programmable external bus cycle lengths, and the programmable multiplier/divisor of the oscillator input. The fact that they execute code at what would, on a "standard" 805x, be 396 MHz, is a benefit, though, when needed.

There are many vendors of 805x soft cores intended for ASIC or FPGA implementation who make wild claims, omitting, of course, that to attain the claimed performance, the FPGA must use little of its remaining logic, no external memory, etc, and that the required FPGA will be quoted at upward of $1000 each in production quantity if you ask Avnet.

These things require VERY careful scrutiny. Please note that the e8051 to which that original post refers allows a "trial" of the core in order to prove it provides satisfactory resource usage and performance.

That's something these guys in Poland don't offer.

RE