Spend more time reading, before to switching to output mode. The first post from you contained this text:


You forwarded the manufacturers claim that the ASIC has 8.1 times faster than a standard 12-clocker at the same clock speed. It was my conclusion that such a claim seemed to indicate that the ASIC could average 1.5 clocks/instruction, making it look like a one-clocker with some instructions requiring more than one clock.

You then implied in the second-to-last sentence that the ASIC could run at up to (at least) 300MHz. Or you at least chose to make a comparison with the ASIC running at that speed.

You then supplied something that very much looks like a claim by you: "In fact, any one-clocker at 25 MHz is as fast as that one at 300 MHz, at first glance."

I haven't claimed any 300MHz, and the Digital Core Design page don't seem to claim any 300MHz, so the figure 300MHz in your suggested comparison seems to be your claim. The web page seems to indicate 100 or 130MHz clock speeds for the ASIC, so the figure 300MHz did confuse me, but I decided to follow up your (yes, very much seems to be your) claim.

Since the manufacturers claim would have resulted in > 200 MIPS at 300 MHz (or possibly even 300 MIPS just counting NOP instructions if it is a one-clocker and the figure 8.1x faster is a weighted average from a certain set of instructions), I started to wonder how the ASIC would require 300 MHz operating speed just to be able to match "any one-clocker" running at 25 MHz. For a 300MHz ASIC to manage the same number of NOP/s, it would require 12 clock cycles for each NOP, which is 8 times slower than the manufacturer seems to claim.

The manufactuers claims seem to indicate that DT8051 is similar to a one-clocker, so how come you need to overclock the ASIC 2.5-3 times, or the STRATIX-III 1.5 times to get 25 MIPS NOP instructions?

Now, instead of throwing around bad comments like "No ... it's 1 MIPS at 12 MHz. That's what 12-clocker means.", maybe you could explain exactly what meant by "first glance"?

Was your "first glance" decision that any 25MHz one-clocker is the same speed as a 300 MHz ASIC the result of an initial test run done by you? Or by a test done by someone else? Or the result of a computation you did, based on any figures I haven't noticed on that web page or somewhere else?

It was because YOU did the claim that the 25MHz one-clocker was the same effective speed, when the manufactures claim seemed to indicate that they shouldn't even be close, that I started my post with: "I probably misunderstood something but: [...]" It was a request that you would refine your presentation, so we could know how you get to your conclusion.

If I did misunderstood something in that post of yours (and it was not the definition of a 12-clocker) then maybe you could supply a bit more information about why a 25MHz one-clocker has the same effective speed as a 300MHz ASIC.


No, I did not do that assertion. I just noted that your post seemed to indicate an ASIC consuming between 1 and 2 clocks/instruction, and it seemed to indicate that the ASCI would run at 300MHz, or at least require 300MHz to be comparable to "any 25MHz one-clocker". I then wanted to know why the ASIC at 300 MHz still would not manage better than 25 million NOP/second. In short, I was very confused about the figures in your post, in relation to your claim in the post, and in relation to the information on the manufactuers page and wanted more clarifying information.

Having an ASIC at 300 MHz run the same speed as "any 25MHz one-clocker" would imply that the ASIC was consuming 12 clocks/instruction, since 300MHz/12 => 25 MIPS. After all, this seems very much to be your claim, as represented by:


But I know. Instead of respond to other peoples questions and notes, you will either ignore comments, or you will make your best to run away in a totally different direction, somehow trying to move the focus away from the original comment.

I have never said that I have believed any claims about the DT8051 - especially not claims that the manufactuer don't seem to have made.

I have never produced new claims about the DT8051, just simple computations showing that I have a problem getting your claims to make sense.

So:

Is the ASIC implementation a 12-clocker, requiring 12MHz clock frequency to match the original 8051 (meaning that the manufactuers 8.1x is totally bogus with a factor 8.1)?

Is the ASIC implementation a 12-clocker, requiring 300MHz clock frequency to match a 25MHz one-clocker (meaning that the manufactuers 8.1x is totally bogus with a factor 8.1)?

Are there any facts anywhere on the net substantiating that the ASIC at 300MHz can't beat a 25MHz one-clocker?

Where did the figure 300MHz in your post come from, given the figures of 100MHz/130MHz on the manufactuers page for ASIC, and 210MHz using an ALTERA STRATIX III?