There are numerous opportunities for concurrent and out-of-order execution of instructions in 805x instruction set. There are also techniques that can be applied to shorten the execution of multi-byte instructions, and both of these methodologies can take advantage of a "wide view" of the code space. Instructions that affect the operand of an immediately subsequent instruction are not good candidates for concurrent execution, as the interaction would drive the code "into the weeds," but there are ample cases where an instruction affects only its own operand and not that of its immediate successor. Further, instructions such as MOV DPTR, #AAAA affect only the DPTR. There's no reason that can't be executed concurrently with a LJMP, ACALL, or other instruction that doesn't rely on or affect the DPTR.

Hardware commonly present in FPGA can reduce the length of MUL and DIV instructions, and FPGA can be used to present the code space in, say, 48-bit width.

All of these things can increase the execution speed of a single-oscillator cycle-per-system-clock-cycle MCU. It doesn't even make the performance of the MCU unpredictable, once the code is written. Quite frankly, I don't see why it hasn't been done and published yet. It's not rocket-science.

RE