| ??? 05/05/09 15:26 Read: times |
#165068 - It's confusing ... typical marketing drivel Responding to: ???'s previous message |
Per Westermark said:
I probably misunderstood something but:
Richard said:
but that one intended for ASIC claims it's 8.1 times faster than the standard 805x at the same crystal frequency. The SiLabs 'F12x's and Maxim/Dallas DS89c4x0's are certainly capable of more speed. In fact, any one-clocker at 25 MHz is as fast as that one at 300 MHz, at first glance. Not very impressive! But a bit simplified: The standard 805x is a 12-clocker, and they claim 8.1x faster speed at the same clock frequency. So a 25MHz one-clocker would do about 25 MIPS? Well, a 1-clocker is claimed by several vendors to be 12x as fast as the "standard." The 33 MHz DS89C420, the original Maxim/Dallas one-clocker, was claimed to execute at 1 MIPS/MHz. I know that's based on how it executes NOP's, which is one of the many de-facto standards for execution rate. So a 25 MHz one-clocker would, presumably, execute at 25 MIPS, and a 12 clocker would have to run at 12x that rate, (12x25=300) to match it. I'm not sure where they'd get that 8.1, based on their other numbers, unless they made some computations based on average instruction mix. Their claim about Dhrystone 2.1 may provide a clue. If you believe their claim that they're 8.1 times as fast as a standard 805x at the same crystal frequency, it tells you one thing. If you believe their claim of 300 MHz it's another. Which is it? And a 300MHz ASIC running 8.1 times faster than a 12-clocker at the same clock speed would do about 300*8.1/12=217 MIPS at 300MHz and about 12*8.1/12 = 8.1 MIPS at 12MHz? No ... it's 1 MIPS at 12 MHz. That's what 12-clocker means. In reality, it's considerably less than (1 MIPS)/(12 MHz) since many frequently used instructions are longer than one system clock cycle. I imagine they use the 12-clock scheme to maintain compatibility with "standard" peripherals, e.g. timers/UART, etc. If you say that a 25MHz one-clocker is the same speed as this ASIC implementation is at 300Mhz, then you are saying that the ASIC implementation is a 12-clocker. But such a claim would be incompatible with any claim that it is 8.1 times faster than the standard 805x at the same crystal frequency - the claim would then be that it is the same speed as a standard 805x at the same crystal frequency.
The 8.1 times claim sounds to me like the ASIC implementation is averaging just under 1.5 clocks/MIPS - a weighted average between one-clock and two-clock instructions depending on the mix of instructions. If the solution can do 217 MIPS with a reasonable power consumption, then I would think that quite impressive. Yes it's quite impressive, but it's not exactly what they claim. It's really not clear at all what the claim is. At one point they say "8.1 times faster than standard 80C51 at the same frequency " and "Dhrystone 2.1 benchmark program runs exactly 8.1 times faster than the original 80C51 at the same frequency" They never do get around to explaining the relationship between their 300 MHz claim and their 8.1x speed claim. Are they hiding something? One thing they do indicate, with respect to FPGA, is XILINX SPARTAN-3E speed grade -5 using 1029 0 / 11721 Slices yields 75 MIPS with no DoCD debugger or 75 MIPSin the compact DoCD version includes processor execution control (run, halt, reset, step); read-write all processor content (PC, SFRs); read-write all processor memories (IDATA, XDATA, CODE memory); FLASH code memory programming; one hardware code execution breakpoint; unlimited number of OPCODE execution breakpoints That's not "top" speed for the technology, though it's quite close. I'm willing to believe, based on the aggregate of all the numbers rather curiously scattered about their datasheet and marketing brocheure, that it's capable of impressive speed in ASIC, but I'm also persuaded that their numbers are more for entertainment than for information. RE |
