The two things are mixed in my optinion:

1. Architecture speed improvement - it doesn't depend on MHz. It is a feature which decides how fast certain architecture can run Dhrystone v2.1 (in this case) if we'd run both of them (compiled identically by the same C compiler) at the same CLK frequency. So in case of DT8051 vs 80C51 we have 8.1 and it does not depend on MHz. This factor is constant no matter if we apply 1 kHz or 12 MHz to both CPUs. Let me know if I'm wrong. This comparison make sense because both architectures execute identical 255 binary opcodes.

2. Maximum real CLK frequency - it is the real value applied to CLK pin of both architectures (DCD's DT8051 and Intel's 80C51). So assuming that Intel 80C51 can run 12 MHz, and DCD's DT8051 can run 200 MHz in Virtex-5 FPGA, we know that Dhrystone program executes 200MHz/12MHz= 16.67 times shorter because of different CLK, and additionally 8.1x shorter because of architecture speed. So final factor for Dt8051 is 135.0 times shorter than 80C51. But this is because of different CLK frequencies. In case when we'd apply 200 MHz to Intel 80C51 (of course theoretically) then we have again 8.1x factor for DT8051 vs 80C51. I hope it is clear and doesn't contain any stupid mistake.

Please correct me if I'm wrong in those two statements.